1. Field
The present invention generally relates to the field of semiconductor devices, and more specifically to erasable programmable read-only memories.
2. Background
An EPROM, or Erasable Programmable Read-Only Memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in electronic circuits. Floating gate transistors commonly comprise a floating control gate isolated by a thin oxide layer. When a floating gate is given an electrical charge, that charge is trapped by the insulating thin oxide layer through a process known as Hot Electron Injection. Once programmed, a traditional EPROM can be erased only by exposing it to strong ultraviolet light through a transparent window in the top of the package. As the glass window is expensive to make, OTP (one-time programmable) chips were introduced; the only difference is that the EPROM chip is packed in an opaque package, so it cannot be erased after programming.
For a number of reasons, it may be useful for an EPROM to have an indicator as to whether it has ever been programmed. For example, a test engineer may want to know whether the current part that he or she is working on is a fresh part or whether it has been worked on. This could be because different lots may be trimmed at different locations.
Ideally, this indicator could just be a program status bit on the EPROM itself. Unfortunately, previous EPROM designs do not provide for a means of guaranteeing that the logic state of a particular bit will always be the same on every part just after fabrication but prior to programming. FIG. 1 shows a schematic for one bit of a common EPROM design. In this design, the logic state of the bit is defined by a differential between the magnitudes of two currents, IA and IB. For instance, if the magnitude of IA is less than IB, the bit will be logic 0 at output 120, and if IB is less than IA, the bit will read logic 1 at output 120. The differential is sensed by latching circuit 110. The magnitude of each current is determined by the amount of charge on their respective floating gates, MA and MB. The initial state of the bit is set by charge deposition onto these floating gates during final anneal and capacitive coupling to other nodes. Typically, this results in IA and IB being approximately equal to each other, but for slight variations due to device mismatch. Therefore, the initial state of the bit is effectively determined by the mismatch, and there is an equal possibility of the bit's unprogrammed value being logic 1 or logic 0. As such, the previous designs do not provide a means of guaranteeing that the logic state of a particular bit will always be the same after fabrication but prior to programming.